module mux5_1b(x,y,w,u,v,m,s0,s1,s2);
	input [2:0] x,y,w,u,v;
	input s0,s1,s2;
	output reg [2:0] m;
	always @(*)
	begin
		case({s2,s1,s0})
			3'b000: m=u;
			3'b001: m=v;
			3'b010: m=w;
			3'b011: m=x;
			3'b100: m=y;
			3'b101: m=y;
			3'b110: m=y;
			3'b111: m=y;
		endcase
	end
endmodule